IRATI D3.2 “2nd phase RINA prototype over Ethernet for a UNIX-like OS” available
IRATI’s deliverable D3.2, informing about the second phase prototype of a RINA implementation for a UNIX-like OS (focusing in the general updates to the first phase prototype, the implementation of EFCP, the PDU Forwarding Table Generator and the porting of user-space components to C++), has been uploaded to the Deliverables area.
This document presents the IRATI project second phase integrated RINA prototype over Ethernet for a UNIX-like prototype. This prototype – as well as its companion D3.3 – provides the functionalities required for the second phase experimentation activities (ref. D2.3) and has been released to WP4.
Given the extensible software architecture and clean design of the whole IRATI stack, the new functionalities have been incrementally introduced into the first phase prototype. No modifications have been required to its lower level kernel parts – e.g. the shims, the IPC Process factories. Even the configuration, building and development environments remained almost untouched, with only minor changes due to the integration of the new functionalities. Therefore, both the high-level architecture and the software design documents previously released – i.e. D2.1, D3.1 and D2.3 – still hold. This document presents only the (slight) adaptations made to the second phase high level design document as well as the software detailed design of the prototype. Moreover, since functionalities introduced for deliverable D3.3 reside at different levels, they can be intermixed with the ones presented in this document without any change.
This document is structured as follows. Section 1 provides introductory notes and motivations backing the approaches described in the remaining sections. Section 2 presents the design and implementation details of the reliable-flows related code introduced into the stack. Section 3 describes the link-state routing policy introduced in the PDU Forwarding Table Generator. Section 4 addresses the implementation of the PDU’s PCI serialisation and deserialisation procedures. Section 5 describes the details of porting, from Java to C++, both the IPC Process and the IPC Manager daemons. Finally, section 6 outlines the outcomes of the works performed in the previous sections as well as providing some insights on future works that might be eventually executed during the project’s third phase and described in the upcoming D3.4.